Tire (Bus) is the entire set of lines (conductors on the motherboard) through which PC components and devices exchange information. Buses are designed to exchange information between two or more devices. A bus that connects only two devices is called port. In Fig. 1 shows the bus structure.

The bus has places for connecting external devices – slots, which as a result become part of the bus and can exchange information with all other devices connected to it.

Rice. 1. Bus structure

Buses in PC differ in their functional purpose :

• system bus(or CPU bus) is used by Cipset chips to send information to and from (see also Fig. 1);
• tire designed to exchange information between the CPU and cache memory (see also Fig. 1);
• memory bus used to exchange information between RAM and CPU;
• I/O buses information is divided into standard and local.

Local I/O bus is a high-speed bus designed for exchanging information between high-speed peripheral devices (video adapters, network cards, scanner cards, etc.) and the system bus controlled by the CPU. Currently, the PCI bus is used as the local bus. To speed up video input/output and improve PC performance when processing 3D images, Intel developed the AGP bus ( AcceleratedGraphicsPort).

Standard I/O bus used to connect slower devices (for example, mice, keyboards, modems, old sound cards) to the buses listed above. Until recently, the ISA standard bus was used as this bus. Currently it is a USB bus.

The bus has its own architecture, which makes it possible to implement its most important properties - the ability to parallel connect an almost unlimited number of external devices and ensure the exchange of information between them. The architecture of any bus has the following components:

• lines for data exchange (data bus);
• lines for addressing data (address bus);
• data control lines (control bus);
• bus controller.

Controller The bus controls the processor for data exchange and service signals and is usually implemented in the form of a separate chip or in the form of a compatible chipset - Chipset.

Data bus provides data exchange between the CPU, expansion cards installed in the slots, and RAM memory. The higher the bus width, the more data can be transferred per clock cycle and the higher the PC performance. Computers with an 80286 processor have a 16-bit data bus, computers with an 80386 and 80486 CPU have a 32-bit data bus, and computers with a Pentium family CPU have a 64-bit data bus.

Read our lecture!

Address bus serves to indicate the address to any PC device with which the CPU exchanges data. Each PC component, each I/O register and RAM cell has its own address and is included in the general address space of the PC. An identification code is transmitted via the address bus ( address) sender and (or) recipient of the data.

To speed up data exchange, an intermediate data storage device is used - RAM – RAM. In this case, the amount of data that can be temporarily stored in it plays a decisive role. Volume depends on the address bus width(number of lines) and thus from the maximum possible number of addresses generated by the processor on the address bus, i.e. on the number of RAM cells to which an address can be assigned. The number of RAM cells should not exceed 2n, where n– address bus width. Otherwise, some cells will not be used because the processor will not be able to address them.

In the binary number system, the maximum addressable memory size is 2n, where n– number of address bus lines.

The 8088 processor, for example, had 20 address lines and could thus address 1 MB of memory (2 20 = 1,048,576 bytes = 1024 KB). In PCs with the 80286 processor, the address bus was increased to 24 bits, and the 80486, Pentium, Pentium MMX and Pentium II processors already have a 32-bit address bus, with which you can address 4 GB of memory.

Control bus transmits a number of service signals: write/read, readiness to receive/transmit data, confirmation of data receipt, hardware interrupt, control and others to ensure data transmission.

Main characteristics of the tire

Bus width determined by the number of parallel conductors included in it. The first ISA bus for the IBM PC was eight-bit, i.e. it could transmit 8 bits simultaneously. The system buses of modern PCs, for example, Pentium IV, are 64-bit.

Bandwidth tires determined by the number of bytes of information transferred over the bus per second.

When calculating the throughput of, for example, the AGP bus, you should take into account its operating mode: by doubling the clock frequency of the video processor and changing the data transfer protocol, it was possible to increase the bus throughput by two (2 x mode) or four times (4 x mode), which is equivalent to increasing the bus clock frequency by a corresponding number of times (up to 133 and 266 MHz, respectively).

External devices are connected to the buses via interface (Interface– pairing), which is a set of various characteristics of a PC peripheral device that determine the organization of information exchange between it and the central processor.

Such characteristics include electrical and timing parameters, a set of control signals, a data exchange protocol and design features of the connection. Data exchange between PC components is only possible if the interfaces of these components are compatible.

PC bus standards

The principle of IBM compatibility implies standardization of the interfaces of individual PC components, which, in turn, determines the flexibility of the system as a whole, i.e. the ability to change the system configuration and connect various peripheral devices as necessary. In case of interface incompatibility, controllers are used. In addition, flexibility and system unification are achieved through the introduction of intermediate standard interfaces, such as those required for the operation of the most important input and output peripherals.

System bus designed to exchange information between the CPU, memory and other devices included in the system. System buses include:

• GTL, which has a bit depth of 64 bits, a clock frequency of 66, 100 and 133 MHz;
• EV6, the specification of which allows you to increase its clock frequency to 377 MHz.

Tires are being improved in line with the development of PC peripherals. In table Figure 2 shows the characteristics of some I/O buses.

TireISA was considered a PC standard for many years, but is still retained in some PCs today along with the modern PCI bus. Intel, together with Microsoft, has developed a strategy to phase out the ISA bus. At the beginning, it is planned to eliminate ISA connectors on the motherboard, and subsequently eliminate ISA slots and connect disk drives, mice, keyboards, scanners to the USB bus, and hard drives and CD-ROM drives to the IEEE 1394 bus. However, the presence of a huge fleet of PCs with the ISA bus will be in demand for some time to come.

Tire EISA became a further development of the ISA bus in the direction of increasing system performance and compatibility of its components. The bus is not widely used due to its high cost and bandwidth, which is inferior to that of the VESA bus that appeared on the market.

table 2. I/O Bus Specifications

Tire	Depth, bits	Clock frequency, MHz	Bandwidth, MB/s
ISA 8-bit	08	8,33	0008,33
ISA 16-bit	16	8,33	0016,6
EISA	32	8,33	0033,3
VLB	32	33	0132,3
PCI	32	33	0132,3
PCI 2.1 64-bit	64	66	0528,3
AGP (1 x)	32	66	0262,6
AGP (2 x)	32	66x2	0528,3
AGP (4 x)	32	66x2	1056,6

Tire VESA , or VLB , designed to connect the CPU with fast peripheral devices and is an extension of the ISA bus for exchanging video data.

Tire PCI was developed by Intel for the Pentium processor and is a completely new bus. The fundamental principle underlying the PCI bus is the use of so-called bridges, which communicate between the PCI bus and other types of buses. The PCI bus implements the Bus Mastering principle, which implies the ability of an external device to control the bus when sending data (without the participation of the CPU). During information transfer, a device that supports Bus Mastering takes over the bus and becomes the master. In this case, the central processor is freed up to handle other tasks while data is being transferred. In modern

On motherboards, the PCI bus clock frequency is set as half the system bus clock frequency, i.e. With a system bus clock speed of 66 MHz, the PCI bus will operate at 33 MHz. Currently, the PCI bus has become the de facto standard among I/O buses.

Tire AGP – high-speed local input/output bus designed exclusively for the needs of the video system. It connects the video adapter (3D accelerator) with the PC memory system. The AGP bus was designed based on the PCI bus architecture, so it is also 32-bit. However, it has additional opportunities to increase throughput, in particular through the use of higher clock speeds.

Tire USB was developed by leaders in the computer and telecommunications industry Compaq, DEC, IBM, Intel, Microsoft for connecting peripheral devices outside the PC case. The speed of information exchange via the USB bus is 12 Mbit/s or 15 MB/s. To computers equipped with a USB bus, you can connect peripheral devices such as a keyboard, mouse, joystick, and printer without turning off the power. All peripheral devices must be equipped with USB connectors and connected to the PC through a separate remote unit called USB hub , or hub , with which you can connect up to 127 peripheral devices to your PC. The architecture of the USB bus is shown in Fig. 4.

Tire SCSI (SmallComputerSystemInterface) provides data transfer speeds of up to 320 MB/s and allows for connection to one adapter of up to eight devices: hard drives, CD-ROM drives, scanners, photo and video cameras. A distinctive feature of the SCSI bus is that it is a cable loop. The SCSI bus is connected to PC buses (ISA or PCI) via host adapter (HostAdapter). Each device connected to the SCSI bus can initiate communication with other devices.

Tire IEEE 1394 – This is a high-speed local serial bus standard developed by Apple and Texas Instruments. The IEEE 1394 bus is designed to exchange digital information between

PCs and other electronic devices, especially for connecting hard drives and audio and video processing devices, as well as running multimedia applications. It is capable of transferring data at speeds of up to 1600 MB/s, working simultaneously with several devices transmitting data at different speeds, just like SCSI.

Almost any device capable of working with SCSI can be connected to a computer via the IEEE 1394 interface. These include all types of disk drives, including hard drives, optical drives, CD-ROMs, DVDs, digital video cameras, and devices. Thanks to such wide capabilities, this bus has become the most promising for combining a computer with consumer electronics. IEEE 1394 adapters for the PCI bus are currently being produced.

4 / 5 ( 4 votes)

By helping the BEST-EXAM project, you make education more accessible to every person, make your contribution too -
share this article on social networks!

The performance of the entire system depends on them. On the motherboard for each device - disk drives, etc. there is a control electronic circuit - an adapter, or controller. Some controllers can control multiple devices at once.

All computer controllers interact with the processor and through the system data transfer bus, which is also called the system tire. In addition to the system bus, modern motherboards have several buses and corresponding connectors for connecting devices:

1. memory bus – for exchanging information between RAM and the central processor;
2. AGP bus – for connecting a video adapter.
3. cache memory bus - for exchanging information between the cache memory and the central processor;
4. I/O buses (interface buses) – used to connect various devices.

There are three main indicators of computer bus operation: clock speed, bit depth, data transfer rate or throughput.

The operation of any computer depends on the clock frequency determined by a quartz oscillator, which is a tin container with a quartz crystal placed in it. Under the influence of electrical voltage, electrical vibrations occur in the crystal. The frequency of these oscillations is called the clock frequency. All changes in logical signals in any computer chip occur at certain time intervals, called clock cycles. Thus, the smallest unit of time for most computer logic devices is the clock period. Each operation requires at least one clock cycle, although some modern devices manage to perform several operations in one clock cycle. The clock speed of a computer is measured in megahertz (MHz or GHz). There are so-called empty clocks (waiting cycles) when a device is in the process of waiting for a response from some other device. This is how the work of RAM and the computer processor is organized, the clock frequency of which is significantly higher than the clock frequency of RAM.

Buses use multiple channels to transmit electrical signals. If 32 channels are used, then the buses are considered 32-bit, if 64 channels are used, then the buses are 64-bit. In reality, buses of any width have a larger number of channels. Additional channels are designed to transmit specific information.

Each computer bus differs from a simple conductor in that it has three types of lines: data lines, address lines, control lines.

The data bus exchanges between the central processor, expansion cards installed in slots, and the computer's RAM.

The process of data exchange is possible only if the sender and recipient of this data are known. Each component of a personal computer has its own address and is included in the general address space. To address a device, an address bus is used, through which the unique address of the device is transmitted. The maximum amount of RAM depends on the width of the computer's address bus (number of lines) and is equal to 2 to the power of n, where n is the number of lines of the address bus. For example, computers with an 80486 processor or higher have a 32-bit address bus that can address 4 GB of memory.

To successfully transfer data over the bus, it is not enough to install it on the data bus and set the address on the address bus. A number of service signals are also required, which are transmitted via the computer control bus.

The speed of each computer bus is characterized by its throughput, the maximum possible transmitted on the bus per unit of time, and is measured in MB/s or GB/s. The bus bandwidth is determined by the product of the data line width and the clock frequency. The higher the throughput, the higher the performance of the entire system.

In reality, the throughput of a computer bus is affected by many different factors: ineffective conductivity of materials, design and assembly flaws, and much more. The difference between the theoretical data transfer speed and the practical one can be up to 25%.

It was eight-bit, i.e. it could simultaneously transmit 8 bits. The system buses of modern PCs, for example, Pentiurr IV, are 64-bit.

The bus throughput is determined by the number of bytes of information transmitted over the bus per second. To determine the bus bandwidth, it is necessary to multiply the bus clock frequency by its bit depth. For example, for a 16-bit ISA bus, the bandwidth is defined as follows:

(16 bits * 8.33 MHz): 8 = 16.66 MB/s.

When calculating the throughput of, for example, the AGP bus, you should take into account its operating mode: by doubling the clock frequency of the video processor and changing the data transfer protocol, it was possible to increase the bus throughput by two (2x mode) or four times (4* mode), which is equivalent to increasing the bus clock frequency by the corresponding number of times (up to 133 and 266 MHz, respectively).

External devices are connected to the buses through an interface (Interface - pairing), which is a set of various characteristics of a PC peripheral device that determine the organization of information exchange between it and the central processor.

Such characteristics include electrical and timing parameters, a set of control signals, a data exchange protocol and design features of the connection. Data exchange between PC components is only possible if the interfaces of these components are compatible.

PC bus standards

The principle of IBM compatibility implies standardization of the interfaces of individual PC components, which, in turn, determines the flexibility of the system as a whole, i.e. the ability to change the system configuration and connect various peripheral devices as necessary. In case of interface incompatibility, controllers are used. In addition, flexibility and unification of the system are achieved through the introduction of intermediate standard interfaces, such as serial and parallel data transfer interfaces. These interfaces are necessary for the operation of the most important input and output peripheral devices.

The system bus is designed to exchange information between the CPU, memory and other devices included in the system.

System buses include:

GTL, which has a bit depth of 64 bits, a clock frequency of 66, 100 and 133 MHz;

EV6, the specification of which allows you to increase its clock frequency to 377 MHz.

I/O buses are being improved in line with the development of PC peripherals. In table 2.5 shows the characteristics of some input/output buses.

ISA bus was considered a PC standard for many years, but is still retained in some PCs today along with the modern PCI bus. Intel, together with Microsoft, has developed a strategy to phase out the ISA bus. Initially, it is planned to eliminate the ISA connectors on the motherboard, and subsequently eliminate the ISA slots and connect disk drives, mice, keyboards, scanners to the USB bus, and hard drives, CD-ROM, DVD-ROM drives to the NEC 1394 bus. However, the presence of a huge A couple of PCs with an ISA bus and corresponding components suggest that the 16-bit ISA bus will be in demand for some time to come.

EISA bus became a further development of the ISA bus in the direction of increasing system performance and compatibility of its components. The bus is not widely used due to its high cost and bandwidth, which is inferior to the VESA bus that appeared on the market.

VESA bus, or VLB, designed to connect the CPU with fast peripheral devices and is an extension of the ISA bus for exchanging video data. When the CPU 80486 processor dominated the computer market, the VLB bus was quite popular, but has now been replaced by the more powerful PCI bus.

PCI bus was developed by Intel for the Pentium processor and is a completely new bus. The fundamental principle underlying the PCI bus is the use of so-called bridges, which communicate between the PCI bus and other types of buses. The PCI bus implements the Bus Mastering principle, which implies the ability of an external device to control the bus when sending data (without the participation of the CPU).

During information transfer, a device that supports Bus Mastering takes over the bus and becomes the master. In this case, the central processor is freed up to perform other tasks while data is being transferred. In modern motherboards, the PCI bus clock frequency is set as half the system bus clock frequency, i.e. with a system bus clock frequency of 66 MHz, the PCI bus will operate at a frequency of 33 MHz. Currently, the PCI bus has become the de facto standard among I/O buses. In Fig. 2.6 shows the PCI bus architecture

AGP bus— high-speed local input/output bus, designed exclusively for the needs of the video system. It connects the video adapter (ZO accelerator) with the PC system memory. The AGP bus was designed based on the PCI bus architecture, so it is also 32-bit. However, at the same time, it has additional opportunities to increase throughput, in particular, through the use of higher clock frequencies.

If in the standard version the 32-bit PCI bus has a clock frequency of 33 MHz, which provides a theoretical PCI throughput of 33 x 32 = 1056 Mbit / s = 132 MB / s, then the AGP bus is clocked by a signal with a frequency of 66 MHz, so its throughput is 1x mode is 66 x 32 = 264 MB/s; in 2x mode, the equivalent clock frequency is 132 MHz, and the bandwidth is 528 MB/s; in 4x mode the throughput is about 1 GB/s.

USB bus was developed by leaders in the computer and telecommunications industry Compaq, DEC, IBM, Intel, Microsoft for connecting peripheral devices outside the PC case. The speed of information exchange via the USB bus is 12 Mbit/s or 15 MB/s. To computers equipped with a USB bus, you can connect peripheral devices such as a keyboard, mouse, joystick, printer without turning off the power. The TJSB bus supports Plug & Play technology.

When a peripheral device is connected, it is configured automatically. All peripheral devices must be equipped with USB connectors and connected to the PC through a separate remote unit called a USB hub, or hub, with which up to 127 peripheral devices can be connected to the PC. The architecture of the USB bus is shown in Fig. 2.7.

SCSI bus(Small Computer System Interface) provides data transfer speeds of up to 320 MB/s and provides for connecting up to eight devices to one adapter: hard drives, CD-ROM drives, scanners, photo and video cameras. A distinctive feature of the SCSI bus is that it is a cable loop. The SCSI bus is connected to the PC buses (ISA or PCI) through a Host Adapter. Each device connected to the bus has its own identification number (ID). Any device connected to the SCSI bus can initiate communication with another device.

In Fig. Figure 2.8 shows the connection of peripheral devices to a PC using the SCSI bus. There is a wide range of SCSI versions, from the original SCSI I, which provides a maximum throughput of 5 MB/s, to the Ultra 320 version, which provides a maximum throughput of 320 MB/s. The IEEE 1394 bus can compete with the SCSI bus.

IEEE 1394 bus is a high-speed local serial bus standard developed by Apple and Texas Instruments. The IEEE 1394 bus is designed for the exchange of digital information between PCs and other electronic devices, especially for connecting hard drives and audio and video processing devices, as well as multimedia applications. It is capable of transmitting data at speeds of up to 1600 Mbit/s and working simultaneously with several devices transmitting data at different speeds, just like SCSI. Like USB, the IEEE 1394 bus fully supports Plug & Play technology, including the ability to install components without turning off the power to the PC.

Almost any device capable of working with SCSI can be connected to a computer via the IEEE 1394 interface. These include all types of disk drives, including hard drives, optical drives, CD-ROMs, DVDs, digital video cameras, tape recorders, and many other peripherals. Thanks to such wide capabilities, this bus has become the most promising for combining a computer with consumer electronics. IEEE 1394 adapters for the PCI bus are currently being produced.

Questions for students to take notes:

1. Bus definition

2. Purpose of tires

3. Bus architecture

4. The concept of bus width.

5. The concept of bus bandwidth

6. PC bus interface

7. Principle of IBM compatibility

8. Types of tires and their characteristics (fill out the table)

Types of tires	Tire characteristics
Speed	Purpose	Peculiarities	Advantages	Flaws

Introduction

1. Internal tires

1.1.1 PCI Express 1.0

1.1.2 PCI Express 2.0

1.1.3 PCI Express 3.0

1.2 HyperTransport

2. External tires

2.3.1 SATA Revision 2.x

2.3.2 SATA Revision 3.x

2.4 SerialAttachedSCSI

2.4.2 New features in SAS 2.0

Conclusion

List of information sources

Computer bus (from the English computer bus, bidirectional universal switch - bidirectional universal switch) - in computer architecture, a subsystem that transfers data between the functional blocks of the computer. Typically the bus is controlled by a driver. Unlike point-to-point communication, multiple devices can be connected to a bus using a single set of wires. Each bus defines its own set of connectors (connections) for physically connecting devices, cards and cables.

Early computer buses were parallel electrical buses with multiple connections, but the term is now used for any physical mechanism that provides the same logical functionality as parallel computer buses.

The computer bus is used to transfer data between individual functional blocks of the computer and is a set of signal lines that have certain electrical characteristics and information transfer protocols. Buses can differ in capacity, signal transmission method (serial or parallel, synchronous or asynchronous), bandwidth, number and types of supported devices, operating protocol, purpose (internal or interface).

1.1.1 PCI Express 1.0

PCI Express is a computer bus that uses the PCI bus software model and a high-performance physical protocol based on serial data transfer.

The PCI Express serial bus, developed by Intel and its partners, is intended to replace the parallel PCI bus and its extended and specialized variant AGP.

Connecting a PCI Express device uses a bidirectional point-to-point serial connection called a lane; this is in stark contrast to PCI, which connects all devices to a common 32-bit parallel bidirectional bus.

The connection between two PCI Express devices is called a link, and consists of one (called 1x) or more (2x, 4x, 8x, 12x, 16x, and 32x) lane connections. Each device must support 1x connection.

At the electrical level, each connection uses Low Voltage Differential Signaling (LVDS), each PCI Express device sending and receiving information on two separate wires, so in the simplest case, the device connects to the PCI Express switch with just four wires.

Using this approach has the following advantages:

· a PCI Express card fits and works correctly in any slot of the same or greater bandwidth (for example, an x1 card will work in x4 and x16 slots);

· a slot of larger physical size may not be used by all lanes (for example, a 16x slot can be connected to information transmission lines corresponding to 1x or 8x, and all this will function normally; however, it is necessary to connect all the “power” and “ground” lines ", required for slot 16x).

In both cases, the PCI Express bus will use the maximum number of lanes available for both the card and the slot. However, this does not allow the device to work in a slot designed for cards with lower PCI Express bus bandwidth (for example, a x4 card will not physically fit in a x1 slot, even though it could work in a x4 slot using only one lane).

PCI Express sends all control information, including interrupts, over the same lines used for data transfer. The serial protocol can never be blocked, so PCI Express bus latencies are quite comparable to those of the PCI bus. In all high-speed serial protocols (eg GigabitEthernet), timing information must be built into the transmitted signal. At the physical level, PCI Express uses the now generally accepted 8B/10B encoding method (8 bits of data are replaced by 10 bits transmitted over the channel, so 20% of the traffic is redundant), which improves noise immunity.

The PCI bus operates at 33 or 66 MHz and provides 133 or 266 MB/sec of bandwidth, but this bandwidth is shared among all PCI devices. The frequency at which the PCI Express bus operates is 2.5 GHz, which gives a throughput of 2500 MHz / 10 * 8 = 250 * 8 Mbps = 250 Mbps for each PCI Express x1 device in one direction. If there are several lines, to calculate the throughput, the value of 250 Mb/sec must be multiplied by the number of lines and by 2, because PCI Express is a bidirectional bus (Table 1).

Table 1 PCI throughput table.

In addition, the PCI Express bus supports:

· hot replacement of cards;

· guaranteed bandwidth (QoS);

· energy management;

· monitoring the integrity of transmitted data.

1.1.2 PCI Express 2.0

The PCI-SIG released the PCI Express 2.0 specification on January 15, 2007. Key innovations in PCI Express 2.0:

· Increased Bandwidth - The PCI Express 2.0 specification defines the maximum throughput of a single lane connection as 5 Gbps. Improvements have been made to the transfer protocol between devices and the software model.

· Dynamic speed control - to control the speed of communication.

· Bandwidth Alert - to notify software (operating system, device drivers, etc.) about changes in bus speed and width.

· Capability structure extensions - expansion of control registers for better control of devices, slots and interconnect.

· Access Control Services - optional point-to-point transaction management capabilities.

1.1.3 PCI Express 3.0

PCI-SIG introduced version 0.9 of the PCI Express 3.0 specification in mid-August 2010.

For users, the main difference between PCI Express 2.0 and PCI Express 3.0 will be a significant increase in maximum throughput. PCI Express 2.0 has a signal transfer rate of 5 GT/s (gigatransactions per second), which means 500 MB/s of bandwidth per lane. Thus, the main PCI Express 2.0 graphics slot, which typically uses 16 lanes, provides bidirectional throughput of up to 8 GB/s.

With PCI Express 3.0 we will get double these figures. PCI Express 3.0 uses a signal speed of 8 GT/s, which gives a throughput of 1 GB/s per lane. Thus, the main video card slot will receive a throughput of up to 16 GB/s.

At first glance, increasing the signal rate from 5 GT/s to 8 GT/s does not seem like a doubling. However, the PCI Express 2.0 standard uses an 8B/10B encoding scheme.

PCI Express 3.0 moves to a much more efficient 128B/130B encoding scheme, eliminating 20% ​​redundancy. Therefore, 8 GT/s is no longer a “theoretical” speed; This is an actual rate comparable in performance to the 10 GT/s signal rate if the 8b/10b encoding principle were used.

1.2 HyperTransport

The HyperTransport (HT) bus is a bidirectional serial-parallel computer bus with high bandwidth and low latency.

HyperTransport operates at frequencies from 200 MHz to 3.2 GHz (for the PCI bus - 33 and 66 MHz). It also uses DDR, which means data is sent on both the rising and falling edges of the clock signal, allowing for up to 5,200 million transmissions per second at a 2.6 GHz clock frequency; The frequency of the synchronization signal is adjusted automatically.

The HyperTransport bus is based on packet transmission. Each packet consists of 32-bit words, regardless of the physical bus width (number of data lines). The first word in the packet is always the control word. If the packet contains an address, the last 8 bits of the control word are concatenated with the next 32-bit word, resulting in a 40-bit address. The bus supports 64-bit addressing - in this case, the packet begins with a special 32-bit control word indicating 64-bit addressing, and containing address bits 40 to 63 (address bits are numbered starting from 0). The remaining 32-bit words of the packet contain the directly transmitted data. Data is always transmitted in 32-bit words, regardless of their actual length (for example, in response to a request to read one byte, a packet containing 32 bits of data and a flag indicating that only 8 of these 32 bits are significant ).

HyperTransport packets are transmitted sequentially over the bus. An increase in throughput entails an increase in bus width. HyperTransport can be used to transmit system service messages, to transmit interrupts, to configure devices connected to the bus, and to transmit data.

The HyperTransport bus is widely used as a processor bus. It has an original topology (Fig. 1) based on links, tunnels, chains and bridges, which allows this architecture to easily scale. HyperTransport aims to simplify intra-system communications by replacing the existing physical transmission layer of existing buses and bridges, and reduce bottlenecks and latency. With all these advantages, HyperTransport is also characterized by a low pin count and low implementation cost. HyperTransport supports automatic bus width detection, allowing widths from 2 to 32 bits in each direction (Table 2), and it also allows asymmetric data streams to and from peripheral devices.

Tire called a set of lines grouped by functional purpose - address bus (SHA), data bus (SD), control bus (SHU), power bus (SHI).

To characterize a specific tire, you need to describe:

• - a set of signal lines;
• - physical, mechanical and electrical characteristics of the tire;
• - used arbitration, status, control and synchronization signals;
• - rules for interaction of devices connected to the bus (bus protocol).

An important criterion that determines the characteristics of a tire can be its intended purpose. Based on this criterion we can distinguish:

• - processor-memory buses;
• - input/output buses;
• - system buses.

CPU-memory spike

The processor-memory bus provides direct communication between the central processing unit (CPU) of a computer and the main memory (RAM). In modern microprocessors, such a bus is often called front tire and is designated by the abbreviation FSB(Front-Side Bus). Intensive traffic between the processor and memory requires that the bus bandwidth, that is, the amount of information passing along the bus per unit time, be greatest. The role of this bus is sometimes played by the system bus (see below), but in terms of efficiency it is much more profitable if the exchange between the CPU and the OP is carried out on a separate bus. The type under consideration also includes the bus connecting the processor with the second level cache, known as tire rear tan - BSB(Back-Side Bus). BSB allows you to transfer at a higher speed than FSB, and fully realize the capabilities of faster cache memory.

Since in von Nseman machines it is the exchange between the processor and memory that largely determines the performance of the VM, developers pay special attention to the connection between the CPU and memory. To ensure maximum throughput, processor-memory buses are always designed taking into account the specific organization of the memory system, and the bus length is kept as minimal as possible.

I/O bus

I/O bus serves to connect the processor (memory) with input/output devices (I/O). Given the diversity of such devices, I/O buses are unified and standardized. Communications with most airwaves (but not with video systems) do not require high bandwidth from the bus. When designing I/O buses, the cost of the structure and connecting connectors is taken into account. Such buses contain fewer lines compared to the processor-memory option, but the length of the lines can be quite long. Typical examples of such buses are PCI and SCSI buses.

To reduce cost, some VMs have a common bus for memory and I/O devices. This type of bus is often called a system bus. serves to physically and logically combine all VM devices. Because the main components of a machine are typically located on a common circuit board, the system bus is often called the backplane bus, although the terms are not strictly equivalent.

The system bus is capable of containing several hundred lines. The set of bus lines can be divided into three functional groups (Fig. 7.1): data bus, address bus and control bus. The latter usually also includes lines for supplying supply voltage to modules connected to the system bus.

Fig 7.1

The features of each of these groups and the distribution of signal lines are discussed in detail later.

The operation of the system bus can be described as follows. If one of the modules wants to transfer data to another, it must perform two actions: obtain the bus at its disposal and transfer data over it. If a module wants to receive data from another module, it must access the bus and, using the appropriate control lines and address, send a request to the other module. Next, it must wait until the module that received the request sends data.

Physically, the system bus is a collection of parallel electrical conductors. These conductors are metal strips on a printed circuit board. The bus is supplied to all modules, and each of them is connected to all or some of its lines. If the VM is constructed on several boards, then all bus lines are output to connectors, which are then connected by conductors on a common chassis.

Among the standardized system buses of universal VMs, the most famous are Unibus, Fastbus, Futurebus, VME, NuBus, Multibus-II. Personal computers are typically built around a system bus in the ISA, EISA, or MCA standards.

Tire hierarchy

If a large number of devices are connected to the bus, its throughput decreases, since too frequent transfer of bus control rights from one device to another leads to noticeable delays. For this reason, many VMs prefer to use several buses that form a certain hierarchy:

• - a computer with one bus;
• - a computer with two types of buses;
• - a computer with three types of buses.

Single bus computer

In single-bus interconnection structures, there is one system bus that provides information exchange between the processor and memory, as well as between the airborne device, on the one hand, and the processor or memory, on the other.

This approach is characterized by simplicity and low cost. However, a single-bus organization is not able to provide high intensity and speed of transactions, and the bus becomes the bottleneck.

Computer with two types of buses

Although input/output device controllers (IDCs) can be connected directly to the system bus, greater effect is achieved by using one or more I/O buses. UVVs are connected to I/O buses, which carry the main traffic not associated with output to the processor or memory. Bus adapters provide buffering of data when they are sent between the system bus and airborne controllers. This allows the VM to support the operation of multiple input/output devices and simultaneously “decouple” the exchange of information along the processor-memory path and the exchange of information with the airborne device.

This scheme significantly reduces the load on the high-speed processor-memory interface and helps improve the overall performance of the VM. An example is the Apple Macintosh II computer, where the role of the processor-memory bus is played by the NuBus bus. In addition to the processor and memory, some airborne devices are connected to it. Other I/O devices are connected to the SCSI Bus.

Computer with three types of buses

A high-speed expansion bus can be added to the bus system to connect high-speed peripheral devices.

I/O buses are connected to the expansion bus, and from there through an adapter to the processor-memory bus. The circuit further reduces the load on the processor-memory bus. This arrangement of buses is called architecture with an “extension”(mezzanine architecture).